As the processing power and utility of personal computers (PCs) has increased over the years, they have become ubiquitous in business, industry, and the home. With the increase in performance and operating frequency, motherboards in PC systems have become more sensitive to frequency drifts in clock signals.
Many conventional clock generators and frequency timing generation (FTG) products use spread spectrum modulation to reduce electromagnetic interference (EMI) generated. Basically, the output frequency is modulated with a predetermined amplitude (such as 0.5%), a predetermined rate (such as 33 kHz), and a predetermined center frequency (such as −0.25%). One example of a spread spectrum modulation waveform is shown in FIG. 1.
In many conventional systems, spread spectrum modulation is off (i.e., operating in non-spread spectrum mode) at power-up. A user can turn on the spread spectrum modulation via an input pin and/or through an interface, such as the widely used Inter-Integrated Circuit (I2C) interface. When the spread spectrum modulation is turned on, the system is operating in a spread spectrum mode. During the transition from the non-spread spectrum mode to the spread spectrum mode, the phase lock loop (PLL) that generates the clock signal starts trying to lock to the new center frequency and overshoot and/or undershoot may occur. However, excessive frequency overshoot/undershoot may cause failure on the system.
In a conventional PLL, the center PLL frequency (Fpll) is determined by a reference frequency (Fref), a feedback divider value (N), and a reference divider value (M), where (Fpll=N*Fref/M). Different M, N numbers are used for spread spectrum mode and non-spread spectrum mode (M1, N1 and M2, N2, respectively) since the center frequencies in these two modes are generally different.
In many conventional systems, there is no specific technique used to make the transition smoothly. When spread spectrum modulation is off, the PLL is locked to a certain frequency, with certain reference (M1) and feedback (N1) divider values. When a spread spectrum request comes, new reference (M2) and feedback (N2) values are loaded. At about the same time, spread spectrum modulation starts. When the PLL tries to lock to a new center frequency on the top of spread spectrum modulation, it typically causes overshoot and/or undershoot.
FIG. 2 shows a block diagram of one conventional spread spectrum off to spread spectrum on transition circuit. The circuit 200 includes a phase lock loop (PLL) 210, a programmable reference divider 221, a programmable feedback divider 231, two multiplexers 223 and 233, and four registers 225, 227, 235, and 237. The four registers 225, 227, 235, and 237 hold constants associated with either a spread spectrum mode or a non-spread spectrum mode. For instance, register 225 holds a spread off load value (M1), register 227 holds a spread on load value (M2), register 235 holds a spread off load value (N1), and register 237 holds a spread off load value (N2). The programmable reference divider 221 and the programmable feedback divider 231 respectively output a reference signal and a feedback signal to the PLL 210. The PLL 210 generates an output clock signal 209 based on the reference signal and the feedback signal.
When the circuit 200 is in the non-spread spectrum mode, M1 and N1 are loaded into the programmable reference divider 221 and the programmable feedback divider 231, respectively. To start spread spectrum modulation, a spread request signal 201 may be sent to the circuit 200. In response to the spread request signal 201, the multiplexers 223 and 233 load M2 and N2 into the programmable reference divider 221 and the programmable feedback divider 231, respectively.
The direct transition from M1, N1 to M2, N2 while starting spread spectrum modulation at about the same time causes overshoot and/or undershoot as the PLL 210 is trying to settle to a new center frequency. FIG. 3 shows a waveform of a clock signal generated using a conventional spread spectrum off to spread spectrum on transition circuit. There are both overshoot 310 and undershoot 320 in the clock signal generated.